To improve reliability and efficiency of the gateway effectively, a framework composed by FPGA+CPCI control chip was proposed. Based on the hardware design of WTB physical layer and CPCI drive interface, data transceiver of medium attachment unit (MAU) and the timing control of the local bus were introduced in emphasis. According to the standard IEC61375-1, Manchester codec and the data transmission of local bus were realized by introducing finite state machine (FSM), and data read-write of FPGA to CPCI bus was accomplished by state machine transition. Finally, these designs were tested and verified in Quartus II simulation environment, and the results meet the requirements of IEC61375 for frames and timing constraints of local control signals in PCI9030 data book.