1.中南大学 机电工程学院,湖南 长沙 410083
2.中车株洲电力机车研究所有限公司,湖南;株洲 412001
汪炼成(1985—),男,博士,教授,博士生导师,主要从事先进GaN基LED器件和集成系统,IGBT及宽禁带半导体功率模块方面的研究;E-mail: liancheng_wang@csu.edu.cn
扫 描 看 全 文
廖林杰, 范益, 梅晓洋, 等. 基于铜夹互连的双芯片功率器件的热力机械性能研究[J]. 机车电传动, 2023,(5):101-106.
LIAO Linjie, FAN Yi, MEI Xiaoyang, et al. Investigation of thermal-mechanical performance of dual-chip SiC power devices based on Cu clip interconnection[J]. Electric Drive for Locomotives, 2023,(5):101-106.
廖林杰, 范益, 梅晓洋, 等. 基于铜夹互连的双芯片功率器件的热力机械性能研究[J]. 机车电传动, 2023,(5):101-106. DOI: 10.13890/j.issn.1000-128X.2023.05.010.
LIAO Linjie, FAN Yi, MEI Xiaoyang, et al. Investigation of thermal-mechanical performance of dual-chip SiC power devices based on Cu clip interconnection[J]. Electric Drive for Locomotives, 2023,(5):101-106. DOI: 10.13890/j.issn.1000-128X.2023.05.010.
传统的功率半导体器件封装结构通常会采用铝(Al)线键合,这就导致了器件电路寄生电感大和可靠性问题,限制了碳化硅(SiC)功率器件的发展。有研究人员提出了一种新型的铜夹互连工艺,可实现双面散热和提高器件的功率密度,但目前的研究主要集中在其热性能和可靠性方面,缺少对结构设计的优化研究。因此,有必要对多芯片铜夹互连的结构优化设计开展进一步研究。文章针对铜夹功率器件重要的结构参数对芯片应力集中的影响进行了仿真研究。结果表明,铜夹厚度对芯片应力集中影响最大,而铜夹跨度影响最小。对比采用焊料层应力最小的结构参数建立铜夹器件模型与对应的引线模块,可发现在功率循环下,铜夹器件的铜夹和焊料层的疲劳寿命相比于引线模块提升了10倍以上,并且卸荷槽对提升铜夹器件疲劳寿命有显著影响。
Traditional packaging structures of power semiconductor device use aluminum (Al) wire for bonding. This leads to high parasitic inductance and reliability issues, limiting the development of silicon carbide (SiC) power devices. Researchers have proposed a new copper clip interconnection process that enables double-sided heat dissipation and improves the power density of the devices. However, current research mainly focuses on its thermal performance and reliability, lacking exploration of structural design optimization. Further research is necessary to optimize the structure design of multi-chip copper clip interconnections. This study investigated the influence of critical structural parameters of the copper clip power devices on chip stress concentration through simulations. The results indicate that the copper clip thickness has the most significant impact on chip stress concentration, while the copper clip span has the least influence. Optimal structural parameter which was compared with the smallest solder layer stress were used to establish a copper clip device model and the corresponding wire-bonded module. The findings reveal that, under power cycling, the copper clip device shows a more than 10 times improvement in the fatigue life of both the copper clip and solder layer compared with the wire-bonded module. And the unloading groove significantly helps improve the fatigue life of copper clip devices.
铜夹应力集中SiC有限元仿真功率循环
Cu clipstress concentrationSiCfinite element simulationpower cycling
江希. 碳化硅MOSFET坚固性与可靠性研究[D]. 长沙: 湖南大学, 2021.
JIANG Xi. Research on ruggedness and reliability of silicon carbide MOSFET[D]. Changsha: Hunan University, 2021.
柯俊吉. 碳化硅MOSFET芯片并联电气特性及其调控方法研究[D]. 北京: 华北电力大学(北京), 2020.
KE Junji. Electrical characteristics and its control method of paralleled silicon carbide MOSFET chips[D]. Beijing: North China Electric Power University(Beijing), 2020.
中国电子学会生产技术学分会丛书编委会. 微电子封装技术[M]. 2版. 合肥: 中国科学技术大学出版社, 2011.
Compilation Committee of the Production Technology Branch Series of the China Electronics Society. Microelectronics packaging technology[M]. 2nd ed. Hefei: University of Science and Technology of China Press, 2011.
霍炎, 吴建忠. 铜片夹扣键合QFN功率器件封装技术[J]. 电子与封装, 2018, 18(7): 1-6.
HUO Yan, WU Jianzhong. Assembly technology of copper clip bond QFN power device[J]. Electronics & packaging, 2018, 18(7): 1-6.
ZHU Qingwei, FORSYTH A, TODD R, et al. Thermal characterisation of a copper-clip-bonded IGBT module with double-sided cooling[C]//IEEE. 2017 23rd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC). Amsterdam: IEEE, 2017: 1-6.
ROSHANGHIAS A, MALAGO P, KACZYNSKI J, et al. Sinterconnects: all-copper top-side interconnects based on copper sinter paste for power module packaging[J]. Energies, 2021, 14(8): 2176.
CHI Weihao, CHEN H C, LIAO H K. High reliability wire-less power module structure[C]//IEEE. 2018 13th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT). Taipei: IEEE, 2018: 71-74.
TANG Gongyue, WAI L C, LIM T G, et al. Development of high power and high junction temperature SiC based power packages[C]//IEEE. 2019 IEEE 69th Electronic Components and Technology Conference (ECTC). Las Vegas: IEEE, 2019: 1419-1425.
LIANG Zhi, SHAO Dongdong, DING Kunpeng, et al. Design and analysis of MOSFET based on fan-out panel-level package technology[C]//IEEE. 2021 22nd International Conference on Electronic Packaging Technology (ICEPT). Xiamen: IEEE, 2021: 1-4.
WOO D R M, YUAN H H, LI J A J, et al. Miniaturized double side cooling packaging for high power 3 phase SiC inverter module with junction temperature over 220°C[C]//IEEE. 2016 IEEE 66th Electronic Components and Technology Conference (ECTC). Las Vegas: IEEE, 2016: 1190-1196.
LWIN K K, TUBILLO C E, DIMAANO PANUMARD T J, et al. Copper clip package for high performance MOSFETs and its optimization[C]//IEEE. 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC). Singapore: IEEE, 2016: 123-128.
0
浏览量
8
下载量
0
CSCD
0
CNKI被引量
关联资源
相关文章
相关作者
相关机构