Design of Signal Integrality Simulation in High-speed Digital Circuit for DTECS

HOU Chun-yang; LI Long; ZHANG Yong-wei; SHI Li

doi:10.13890/j.issn.1000-128x.2014.04.013

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Design of Signal Integrality Simulation in High-speed Digital Circuit for DTECS

更新时间：2021-12-13

- Design of Signal Integrality Simulation in High-speed Digital Circuit for DTECS
- Electric Drive for Locomotives Issue 4, Pages: 48-52(2014)
- 作者机构：
  
  1. 南车电气技术与材料工程研究院
- 作者简介：
- 基金信息：
- DOI：10.13890/j.issn.1000-128x.2014.04.013
  CLC：
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HOU Chun-yang, LI Long, ZHANG Yong-wei, et al. Design of Signal Integrality Simulation in High-speed Digital Circuit for DTECS. [J]. Electric Drive for Locomotives (4):48-52(2014)
DOI：

HOU Chun-yang, LI Long, ZHANG Yong-wei, et al. Design of Signal Integrality Simulation in High-speed Digital Circuit for DTECS. [J]. Electric Drive for Locomotives (4):48-52(2014) DOI： 10.13890/j.issn.1000-128x.2014.04.013.

摘要

为提高列车分布式网络控制系统的硬件可靠性，对高速数字电路的信号完整性问题进行了仿真研究。首先介绍了信号完整性仿真的方法和工具，然后通过DDR仿真实例，在波形分析、端接匹配分析、串扰分析、同步开关噪声分析等方面，详细论述了信号完整性的仿真策略。试验测试结果表明，测试波形信号完整性良好，仿真结果和测试结果相吻合，验证了该仿真方法的可靠性和实用性。

Abstract

In order to enhance hardware reliability of distribute train electric control system, the signal integrity problems of high-speed digital circuit was simulated and studied. Simulation methods and tools were introduced, and with an example of DDR circuit, signal integrity simulation analysis of wave, matched resistance, crosstalk, and switching noise were discussed in detail. The simulation results and the test results were consistent which verified the reliability of the methods.

关键词

信号完整性高速数字电路DDR端接匹配串扰列车分布式网络控制系统(DTECS)

Keywords

signal integrityhigh-speed digital circuitDDRmatched resistancecrosstalkdistribute train electric control system

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